Course: INP9086599 - ANALOGUE INTEGRATED CIRCUIT DESIGN 2022-2023

Weekly outline

INP9086599 - ANALOGUE INTEGRATED CIRCUIT DESIGN 2022-2023 - PROF. ANDREA NEVIANI

Collapse all Expand all
The "Analogue Integrated Circuit Design" class is offered at the second semester of the first year of the master degree in Electronics Engineering. The aim of the class is to study as well as to try first hand, in the CAD laboratory, the design flow of CMOS integrated circuits for analog applications. The focus of the course is on the building blocks and on the methodologies that are adopted in the design of circuits for analog signal processing (see Integrated Circuits for Signal Processing course) and for radio-frequency applications (see Radiofrequency Integrated Circuit Design course).

In the class, the student will learn how to translate system-level specifications into transistor-level design constraints. Moreover, she will learn how to use at best the degrees of freedoms that come along with the design activity and optimize of one or more parameters such as power consumption, silicon area occupation, noise performance, etc.
- Announcements Forum
- Educational Offer Page URL
- Textbooks and other useful material Page
- Examination and grading Page
- Solutions of a selection of exam problems Folder
- CAD Laboratory Page
- CAD Laboratory: important notices about correct software usage File
- COS 130nm technology parameters for hand calculations File
- CAD Laboratory: summary of MOSFET Short Channel Model equations and V* design methodology File
- LAB01 - Instructions for the live lab session File
- LAB01 - Instructions for the final report File
- LAB02 - Instructions for the live lab session File
- LAB02 - Instructions for the final report File
- LAB03 - Instructions for the live lab session File
- LAB03 - Instructions for the final report File
- LAB04 -Instructions for the live lab session File
- LAB04 - Instructions for the final report File
- Planned schedule of CAD laboratory sessions
  CAD lab sessions take place in room Da, building DEI/D (see map). Since the number of students enrolled (76) exceeds that of available workstations, lab sessions have been split into two shifts, based on the students' surname initial letter. Please, check the date and time of your shift lab sessions in the files below.
  Furthemore, before the first CAD lab session, make sure to check that your CAD environment is set up properly by connecting to the remote server and try the Cadence IC Design Toolset tutorial following the directions given in the CAD laboratory page.
  You are also encouraged to use the Cadence IC Design Toolset connecting to the remote server to practice on your own and create and simulate your own circuits.
  IMPORTANT: as highlighted in the tutorial, a working area has been created for you in /nfsd/cadusers/<your_login_name>. You must use this working area: one of the most common problems with the CAD software is due to students creating the lab working directory right in their home directory, causing their disk quota to reach the upper limit.
- CAD lab shift A-L student list and schedule File
- CAD lab shift M-Z student list and schedule File
27 February - 5 March
- 27/02/2023 - Lecture #01 - Introduction to the course. Recap on MOSFET large-signal and small-signal models.
- Introduction to the course (slides) File
- Recap on MOSFET model (short version) File
- Recap on MOSFET model (long version) File
- 02/03/2023 - Lecture #02 - Recap on MOSFET small-signal figures-of-merit (FoMs). The CMOS common-source stage (CS) revisited.
  I uploaded the complete lecture notes that include algebraic steps and input and output impedance derivation (to be covered in the next lecture).
- L02 - Lecture notes File
- 03/03/2023 - Lecture #03 - Common source stage: input and output impedance. Common gate stage: general topology; input impedance.
- L03 - Lecture notes File
- Week #01 - Reading assignements and problem set
  References to textbooks - MOSFET model: GHLM 1.5, 1.6, 1.8; BR 2.1-2.4. Common source stage: GHLM 7.1–7.2.1; BR 3.3, 6.2
- Y-parameter two-port network model. Miller's theorem File
- Problem set #01 File
- Solution of problem set #01 File
6 March - 12 March
- 06/03/2023 - Lecture #04 - Common gate stage: transfer function, output impedance. Common drain stage: voltage gain, input and output impedance.
- L04 - Lecture notes File
- 09/03/2023 - Lecture #05 - CMOS cascode stage
- L05 - Lecture notes File
- 10/03/2023 - Lecture #06 - Solution of problems
- L06 - Lecture notes File
- Problem set #02 File
- Solution of problem set #02 File
13 March - 19 March
- 13/03/2023 - Lecture #07 - Approximate derivation of an amplifier transfer function through the association of poles with nodes. Introduction to process variation and mismatch
- L07 - Lecture notes File
- L07 - Slides on "Process variation and mismatch in integrated circuits" File
- 16/03/2023 - Lecture #08 - Current mirrors. Basic CMOS current mirror: dc analysis, effect of channel lenght modulation and of device mismatch
- L08 - Lecture notes File
- 17/03/2023 - Lecture #09 - Current mirrors. Basic CMOS current mirror: ac analysis, design guidelines, layout example.
- L09 - Lecture notes File
20 March - 26 March
- 20/03/2023 - Lecture #10 - Cascode current mirror. Problem on current mirror design.
- L10 - Lecture notes File
- L10 - Problem solution File
- 23/03/2023 - Lecture #11 - Differential pair. Large-signal and small-signal analysis
- L11 - Lecture notes File
- 24/03/2023 - Lecture #12 - Fully-differential 5-Transistor OTA. Dc analysis and ac small-signal analysis.
- L12 - Lecture notes File
- Problem set on current mirrors
- Problem set #03 File
- Solution of problem set #03 File
27 March - 2 April
- 27/03/2023 - Lecture #13 - Fully-differential 5-Transistor OTA: frequency behavior of common-mode gain. Single-ended 5-Transistor OTA
- L13 - Lecture notes File
- 30/03/2023 - Lecture #14 - Fully-differential 5-Transistor OTA: offset voltage. Problem solution: design of a SE-5T-OTA (part 1/2).
- L14 - Lecture notes File
- L14 - Problem solution (part 1/2) File
- 31/03/2023 - Lecture #15 - Problem solution: design of a SE-5T-OTA (part 2/2). MOSFET Short Channel Model (SCM). Introduction to V* design methodology.
- L15 - Problem solution (part 2/2) File
- L15 - Lecture notes File
3 April - 9 April
- 03-04/04/2023 - CAD lab session #01 - Design entry and simulation of a SE-5T-OTA.
- LAB01 - Instructions for the live lab session URL
- LAB01 - Instructions for the final report URL
- CAD Laboratory: summary of MOSFET Short Channel Model equations and V* design methodology URL
- 06/04/2023 - Lecture #17 - Review of V* (AKA gm/ID) design methodology. Single-stage OTA's: fully-diffierential, telescopic cascode OTA.
- Summary of MOSFET Short Channel Model equations and V* design methodology URL
- L17 - Lecture notes File
10 April - 16 April
- 13/04/2023 - Lecture #18 - Single-stage OTA's: fully-differential, folded-cascode OTA and current-mirror OTA.
- L18 - Lecture notes File
- 14/04/2023 - Lecture #19 - Exercise: design of a folded-cascode OTA with the V* methodology.
- L19 - Lecture notes File
- CMOS 130nm technology paramenters for hand calculations URL
- Problem set on single-stage OTA's
- Problem set #04 File
- Problem set #04: solution of P1 File
- Problem set #04: solution of P2 File
- Problem set #04: solution of P3 File
17 April - 23 April
- 17-18/04/2023 - CAD lab session #02 - Design of a Fully-Differential Folded-Cascode OTA
- LAB02 - Instructions for the live CAD lab session URL
- LAB02 - Instructions for the final report URL
- 20/04/2023 - Lecture #21 - Two-stage OTA's
- L21 - Lecture notes File
- 21/04/2023 - Lecture #22 - Feedback OTA (part 1)
- L22 - Lecture notes File
24 April - 30 April
- 27/04/2023 - Lecture #23 - Stability of Feedback OTA
- L23 - Lecture notes File
- 28/04/2023 - Lecture #24 - Stability of Feedback OTA (part2). Compensation feedback amplifiers based on single-stage ad two-stage OTA.
- L24 - Lecture notes File
- Problem set on feedback amplifiers
- Problem set #05 File
- Solutions of problem set #05 File
1 May - 7 May
- 04/05/2023 - Lecture #25 - Compensation techniques for feedback amplifiers based on two-stage OTA's (part 2). Exercise.
- L25 - Lecture notes (28/04/2023 + 04/05/2023) File
- L25 - Exercise: analysis of a two-stage OTA with nulling resistor Miller compensation (part 1) File
- 05/05/2023 - Lecture #26 - Exercise: compensation of a two-stage OTA with capacitive feedback (part 2). Introduction to the Return Ratio methodology for the analysis of feedback circuits.
- L26 - Exercise: analysis of a two-stage OTA with nulling resistor Miller compensation (part 1 and 2) File
- L26 -Introduction to the Return Ratio methodology File
8 May - 14 May
- 8 and 12/05/2023 - CAD lab session #03 - Compensation of a two-stage OTA in capacitive feedback configuration
- LAB03 - Instructions for the live lab session URL
- LAB03 - Instructions for the final report URL
- 11/05/2023 - Lecture #28 - Return Ratio methodology for the analysis of feedback circuits. Solution of an exercise on the application of the return ratio method.
- L28 - Lecture notes File
- 12/05/2023 - Lecture #29 - Sample-Data systems. Switched-Capacitor amplifier. Non-linear effects: Slew Rate
- L29 - Lecture notes File
15 May - 21 May
- 15/05/2023 - Lecture #30 - Electronic noise in integrated circuits.
- L30 - Lecture notes (with an additional worked example) File
- 18/05/2023 - Lecture #31 - Solution of a problem on the analysis of a feedback amplifier based on a FC OTA.
- L31 - Problem solution (part 1) File
- 19/05/2023 - Lecture #32 - Solution of a problem on the analysis of a feedback amplifier based on a FC OTA (part 2/2). Solution of a problem on a non-inverting, SC amplifier (part 1/2).
- L32 - Problem on FC-OTA with capacitive feedback (part 1 and 2) File
- L32 - Problem on non-inverting SC amplifier (part 1) File
22 May - 28 May
- 22/05/2023 - Lecture #33 - Solution of a problem on a non-inverting, SC amplifier (part 1 and 2).
- L33 - Problem on non-inverting SC amplifier (part 1 and 2) - updated on 23/05, 12:46 File
- 25/05/2023 - Lecture #34 - Current references: definition of sensitivity; basic topology; VTH-referenced topology; VTH-referenced topology with self bias; VGS-referenced (constant-gm) topology.
- L34 - Current references File
- 26 and 29/05/2023 - CAD lab session #04 - Design of current references
- LAB04 - Instructions for the live lab session URL
- LAB04 - Instructions for the final report URL
29 May - 4 June
- 01/06/2023 - Lecture #35 - Temperature compensation of current and voltage references. Band gap references.
- L35 - Lecture notes File
- 05/06/2023 - Lecture #36 - Solution of past exam problems
- L36 - Lecture notes File

Weekly outline

INP9086599 - ANALOGUE INTEGRATED CIRCUIT DESIGN 2022-2023 - PROF. ANDREA NEVIANI

27 February - 5 March

6 March - 12 March

13 March - 19 March

20 March - 26 March

27 March - 2 April

3 April - 9 April

10 April - 16 April

17 April - 23 April

24 April - 30 April

1 May - 7 May

8 May - 14 May

15 May - 21 May

22 May - 28 May

29 May - 4 June